1. Technical Field
The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device that employs a semiconductor chip in which an internal circuit is formed, a chip tab mounting the semiconductor chip, and encapsulation resin to encapsulate the semiconductor chip and the chip tab.
2. Description of the Background Art
Portable electronic devices such as mobile phones and digital cameras are ubiquitous. The integrated circuits (IC) used in these portable electronic devices are required to be made more compact and with a higher degree of accuracy. Market demand for rigorous accuracy is particularly intense, with some market sectors seeking tolerance guarantees of from 1% to 0.5% or even less. As used herein, the term “tolerance” means deviation in performance of an actually manufactured IC from that of an IC that is formed according to design without dimensional error.
Although it is difficult to treat such tolerances as a whole because there are many different types, in general they can be divided into two major groups depending on the stage of IC manufacture in which they occur.
The first type of tolerance is one that arises during processing of a semiconductor wafer. When the semiconductor wafer is processed and target circuit elements are constructed therein, the dimensions of the circuitry and the degree of impurity may deviate slightly from design values therefor. The first type of tolerance is caused by deviations in processing, which typically follows a normal distribution curve.
The first type of tolerance can be reformed by improving the characteristics of production equipment because the first type of tolerance is caused by processing deviation. In addition, a circuit design method in which a circuit area having a larger size such that processing deviation is not a problem is aggressively used for circuits requiring a high degree of accuracy.
The second type of tolerance is generated when a completed semiconductor wafer is cut into chips and each chip is inserted in a container so-called, a package, as an individuated pack. FIG. 1 is a schematic plan view and a cross-sectional diagram illustrating a conventional semiconductor device (IC) 101. In FIG. 1, reference numerals 103 represents a chip tab, 105 represents a semiconductor chip, 107 represent electrode pads, 109 represent bonding wires, 111 represent leads, and 113 represents encapsulation resin. With reference to FIG. 1, the second type of tolerance is generated when the semiconductor chip 105 cut from the semiconductor wafer is encapsulated by the encapsulation resin 113, and a mechanical stress (hereinafter just “stress”) is exerted on the semiconductor chip 105. This stress, called package stress, skews and deforms the semiconductor chip 105. Owing to the deformation, the electrical characteristics of the circuit elements formed in the semiconductor chip 105 are changed, thereby changing an output signal of the IC 101.
FIG. 2 is a graph illustrating stress exerted on the semiconductor chip 105. In FIG. 2, a vertical axis indicates a stress value (orbital unit), and a horizontal axis indicates a measurement positions representing a distance from a center when the center of the semiconductor chip is set to zero. In the conventional semiconductor device 101, the package stress exerted on the semiconductor chip 105 is largest in a center position thereof and is decreased toward a periphery of the semiconductor chip 105. Since the package stress is simply changed from the center position to the periphery of the semiconductor chip 105, there is no area in which the strength of the package stress is constant.
Several approaches have been proposed for alleviating tolerances arising from package stress. For example, JP H11-145344-A discloses a method that circuit element (e.g., transistor) to be prevented from fluctuation in the electronic characteristics caused by the package stress is arranged in a center position of a chip.
In addition, JP-H10-189875-A discloses a method in which circuit elements (e.g., resistors) to be prevented from fluctuation in electrical characteristics caused by package stress are arranged near a periphery of the chip. In general, the package stress is smallest in the periphery of the semiconductor chip. At the same time, however, localized changes in the package stress are often greatest in the periphery of the semiconductor chip. As a result, fluctuation in the output signal of the IC caused by package stress cannot be solved.
Further, JP-H06-097368-A discloses an approach in which paired circuit elements to be arranged on lines radiating outward from the center (center of gravity) of the chip toward the periphery to equalize package stress. However, this method does not always achieve the expected result, because the strength and the direction of the package stress is affected by the size of the semiconductor chip, the package shape (shape of the encapsulation resin), and the relative positions of the semiconductor chip and the encapsulation resin.
As described above, with the conventional approaches fluctuation in the electrical characteristics of the circuit elements caused by the package stress cannot be eliminated or made uniform, and consequently fluctuation in the output signal caused by the package stress cannot be solved.